Low Power, 3-bit CMOS Pipeline ADC with Reduced Complexity Flash Architecture
نویسندگان
چکیده
A 3-bit, 2-V pipeline analog-to-digital converter has been designed using a modified flash architecture. The developed circuit blocks of the modified flash analog-todigital converter, operating at 135MHz, are a fully differential comparator, a digital-to-analog converter and a sample-and-hold amplifier. The design technique of the N-bit modified flash ADC requires only 2 1) comparators as compared to (2 – 1) comparators used in a standard N-bit flash converter. The final pipeline architecture operates at 80 MHz and consumes a total power of 2.893 mW.
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تاریخ انتشار 2002